// msp430fr2433 with LIS2DH accelerometer // for dementia finger tap testing, work with Raspberry pi // // Hardware configuration: // one SPI interface is used for communicating with LIS2DH accerlerometer // interrupt line from accelerometer is I1 to P1.7 // when accelerometer generates an interrupt in the Raspberry pi, it sets the "drdyFlg" flag // // uses 2nd SPI interface to the raspberry pi with an interrupt line to P2.1 // // Hardware configuration: see hardware.h // // ------------------------------------------------------------------------------------------------- #include #include //allows use of int16_t #define LIS2DH 0x02 //to indicate LIS2DH accelerometer for spi #define cM 16 // for running at 8 MHz (used for multiplying delays) //---------------------------------------------------------------------------- // connections with the LIS2DH //---------------------------------------------------------------------------- //Chip Select for LIS2DH #define CSa_PxSEL P1SEL #define CSa_PxOUT P1OUT #define CSa_PxDIR P1DIR #define CSa_PIN 0x01 //P1.0 : CSn #define STATUS_REG_AUX 0x07 #define OUT_TEMP_L 0X0C #define OUT_TEMP_H 0x0D #define INT_COUNTER_REG 0x0E #define WHO_AM_I 0x0F #define CTRL_REG1 0x20 #define CTRL_REG2 0x21 #define CTRL_REG3 0x22 #define CTRL_REG4 0x23 #define CTRL_REG5 0x24 #define CTRL_REG6 0x25 #define REFERENCE 0x26 #define STATUS_REG2 0x27 #define OUT_X_L 0x28 #define OUT_X_H 0x29 #define OUT_Y_L 0x2A #define OUT_Y_H 0x2B #define OUT_Z_L 0x2C #define OUT_Z_H 0x2D #define FIFO_CTRL_REG 0x2E #define FIFO_SRC_REG 0x2F #define INT1_CFG 0x30 #define INT1_SOURCE 0x31 #define INT1_THS 0x32 #define INT1_DURATION 0x33 #define INT2_CFG 0x34 #define INT2_SOURCE 0x35 #define INT2_THS 0x36 #define INT2_DURATION 0x37 #define CLICK_CFG 0x38 #define CLICK_SRC 0x39 #define CLICK_THS 0x3A #define TIME_LIMIT 0x3B #define TIME_LATENCY 0x3C #define TIME_WINDOW 0x3D #define Act_THS 0x3E #define Act_DUR 0x3F //------------------------------------------------------------------------ char drdyFlg; // flag: LIS2DH is ready with xyz data char accActiveFlg=1; // to indicate if we are getting interrupts from LIS2DH char whoAmIvalue; //value in the LIS2DH who am I register (should return 0x33) unsigned int j; // index to array char zCurr; char zPrev; // z previous reading char zRef; // z reference value @ rest char zDiff; // z Difference, from rest value, or from previous value char aX[3]; // x axis data char aY[3]; // y axis data char aZ[3]; // y axis data int16_t aXi; // signed 12bit data stored in 16 bit signed int16_t aYi; // signed 12bit data stored in 16 bit signed int16_t aZi; // signed 12bit data stored in 16 bit signed char led; // for led value 0-9 unsigned int zCnt; // z counter, int to avoid overflow unsigned int restCnt; //int to avoid overflow unsigned char x; // fast loops, 8 bit value // *************** spi.h ***************** // // subroutines for SPI communication // #define spiReadBit 0x80 #define spiReadBurstbits 0xC0 // ----------------------------------------------------------------------------- // read one register // ------------------------------------------------------------------------------- char spiRreg(char cs, char addr) { char value; CSa_PxOUT &= ~CSa_PIN; // Set CS enabled by setting pin low ie start of transmission //send the address register UCA0TXBUF =addr; //Initiate Transmit characters by transfer into TX buffer //delay required to ensure hardware SPI has time to clock out byte before next byte // note that this could be complier dependent. __delay_cycles(8*2); //assumes SCLK = SPI CLK) min=1 based on fastest compiler option UCA0TXBUF = 0x00; //Initiate Transmit characters by transfer into TX buffer __delay_cycles(8*2); //assumes SCLK = SPI CLK) min 3 cycles based on fastest compiler option value = UCA0RXBUF; // Store data CSa_PxOUT |= CSa_PIN; //disable CS for LIS2DH return value; } //------------------------------------------------- // write one register // ------------------------------------------------- void spiWreg(char cs, char addr, char value) { CSa_PxOUT &= ~CSa_PIN; // Set CS enabled by setting pin low ie start of transmission //send the address register UCA0TXBUF =addr; //Initiate Transmit characters by transfer into TX buffer //delay required to ensure hardware SPI has time to clock out byte before next byte // note that this could be complier dependent. __delay_cycles(8*2); //assumes SCLK = SPI CLK) min=1 based on fastest compiler option UCA0TXBUF = value; //Initiate Transmit characters by transfer into TX buffer __delay_cycles(8*2); //assumes SCLK = SPI CLK) min 3 cycles based on fastest compiler option CSa_PxOUT |= CSa_PIN; //disable CS for LIS2DH } // -------------------------------------------------------------- // fast burst receive multiple bytes // -------------------------------------------------------------- void spiRregs(char cs, char addr, char *buffer, char count) { unsigned int i; CSa_PxOUT &= ~CSa_PIN; // Set CS enabled by setting pin low ie start of transmission UCA0TXBUF =addr; //Initiate Transmit characters by transfer into TX buffer //delay required to ensure hardware SPI has time to clock out byte before next byte // note that this could be complier dependent. __delay_cycles(4*2); //assumes SCLK = SPI CLK) min=1 based on fastest compiler option for (i = 0; i < count; i++) { UCA0TXBUF = buffer[i]; //Initiate Transmit characters by transfer into TX buffer __delay_cycles(8*2); //assumes SCLK = SPI CLK) buffer[i] = UCA0RXBUF; // Store data } CSa_PxOUT |= CSa_PIN; //disable CS for LIS2DH } // ----------------------------------------------------------------- // fast Transmit burst // ----------------------------------------------------------------- // no while statements, testing flags, that could hang the program // no need to test SO line to see if XOSC has started, because that only happens waking up from sleep mode. void spiWregs(char cs, char addr, char *buffer, char count) { unsigned int i; CSa_PxOUT &= ~CSa_PIN; // Set CS enabled by setting pin low ie start of transmission //send the address register UCA0TXBUF =addr; //Initiate Transmit characters by transfer into TX buffer //delay required to ensure hardware SPI has time to clock out byte before next byte // note that this could be complier dependent. __delay_cycles(4*2); //assumes SCLK = SPI CLK) min=1 based on fastest compiler option for (i = 0; i < count; i++) { UCA0TXBUF = buffer[i]; //Initiate Transmit characters by transfer into TX buffer __delay_cycles(4*2); //assumes SCLK = SPI CLK) min 3 cycles based on fastest compiler option } CSa_PxOUT |= CSa_PIN; //disable CS for LIS2DH } //------------------------------------------------------- //VLO=10KHz #define wdt_start (WDTPW + WDTTMSEL + WDTCNTCL + WDTSSEL__VLO + WDTIS__32K); // WDTIS__32K : ~3.27 seconds // *************************** MAIN ********************************* int main(void) { WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer FRCTL0 = FRCTLPW | NWAITS_1; // operation beyond 8MHz requires wait state for memory __bis_SR_register(SCG0); // disable FLL CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source CSCTL0 = 0; // clear DCO and MOD registers CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first CSCTL1 |= DCORSEL_5; // Set DCO = 16MHz CSCTL2 = FLLD_0 + 487; // DCOCLKDIV = 16MHz __delay_cycles(3); __bic_SR_register(SCG0); // enable FLL while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // FLL locked // clock 16 MHz for SMCLK, VLOCLK is 10KHz WDTCTL = wdt_start; // start the Watchdog // configure unused pins/CS/byp to output //P1.4-SIMO : P1.5-SOMI : P1.6-CLK : P1.0-CSa(out) : P1.7 is I1 interrupt P1DIR = 0x0F; //1's indicate unused bits(or required as outputs) for this application P1OUT = 0x0F; // setup the CS lines for LIS2DH, and set them high initially (defined power-on state) P2DIR = 0xFE; //1's indicate unused bits(or required as outputs) for this application P2OUT = 0xff; // init to 0's for example to be off P3DIR = 0x03; //1's indicate unused bits(or required as outputs) for this application P3OUT = 0x03; // init to 1 for LEDs on // configure SPI interface to accelerometer P1SEL0 |= BIT4 | BIT5 | BIT6; // set 3-SPI pin as second function P1REN |= BIT4; //ensure lines at known state and not high impedance P1REN |= BIT5; P1REN |= BIT6; UCA0CTLW0 |= UCSWRST; // **Put state machine in reset** UCA0CTLW0 |= UCMST|UCSYNC|UCCKPL|UCMSB|UCSSEL__SMCLK; // 3-pin, 8-bit SPI master, Clock polarity high, MSB, SMCLK // Max SPI clk for LIS2DH is 10MHz UCA0BR0 = 0x02; // SMCLK = SMCLK/2 which measures 8 MHz SPI clock UCA0BR1 = 0; // baud rate UCA0MCTLW = 0; // No modulation UCA0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine** //configure SPI interface to Raspberry pi P2SEL0 |= BIT4 | BIT5 | BIT6; // set 3-SPI pin as second function P2REN |= BIT4; //ensure lines at known state and not high impedance P2REN |= BIT5; P2REN |= BIT6; UCA1CTLW0 = UCSWRST; // **Put state machine in reset** UCA1CTLW0 |= UCSYNC|UCCKPH|UCMSB; // 3-pin, 8-bit SPI slave, Clock polarity high, MSB UCA1CTLW0 &= ~UCSWRST; // **Initialize USCI state machine** // UCA1IE |= UCRXIE; // Enable USCI_A0 RX interrupt (NO SPI interrupts used for hub) //configure interrupt edges P1IES &= ~(BIT7); // LIS2DH, Int 1 on rising edge // unlock PMMCTL0_H = PMMPW_H; // Unlock the PMM registers PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode // to activate previously configured port settings // delay 5ms to ensure LIS2dH is ready __delay_cycles(40000); //16MHz - 0.0625us*40000 = 2.5ms __delay_cycles(40000); //16MHz - 0.0625us*40000 = 2.5ms __delay_cycles(40000); //16MHz - 0.0625us*40000 = 2.5ms //*********TEST LIS2DH ACCELERATOR - WHO AM I ****************** //try to read register 0x0F "who am I" // 0x0F is the whoamI register, which should return a value of 0x33 whoAmIvalue = spiRreg(LIS2DH, 0x0F | spiReadBit); // can use a program break to test the above value, for hardware troubleshooting // ***************** STARTUP ACC ******************* //5ms setup time for LIS2DH before setting up registers, is met by above delay //setup Accelerometer /* spiWreg(LIS2DH, CTRL_REG1, 0x97); // 1344Hz, Normal Power Mode, XYZ on spiWreg(LIS2DH, CTRL_REG2, 0x00); // HPF bypassed spiWreg(LIS2DH, CTRL_REG3, 0x10); // set DRDY1 interrupt on int1 pin spiWreg(LIS2DH, CTRL_REG4, 0x18); // +/- 4G, and HR mode //spiWreg(LIS2DH, CTRL_REG4, 0x28); // +/- 8G, and HR mode //spiWreg(LIS2DH, CTRL_REG4, 0x38); // +/- 16G, and HR mode spiWreg(LIS2DH, CTRL_REG5, 0x00); // FIFO disabled, no latch spiWreg(LIS2DH, CTRL_REG6, 0x00); // INT2 interrupt disabled */ //setup accelerometer CSa_PxOUT &= ~CSa_PIN; // Set CS enabled for LIS2DH UCA0TXBUF = CTRL_REG1 | 0x40; __delay_cycles(8*2);//assumes SCLK = SPI CLK) min=4 based on fastest compiler option (scoped) UCA0TXBUF = 0x97; __delay_cycles(8*2); // 1344Hz, Normal Power Mode, XYZ on UCA0TXBUF = 0x00; __delay_cycles(8*2); //HPF bypassed UCA0TXBUF = 0x10; __delay_cycles(8*2); // set DRDY1 interrupt on int1 pin UCA0TXBUF = 0x18; __delay_cycles(8*2); // +/- 4G, and HR mode UCA0TXBUF = 0x00; __delay_cycles(8*2); // FIFO disabled, no latch UCA0TXBUF = 0x00; __delay_cycles(8*2); // INT2 interrupt disabled CSa_PxOUT |= CSa_PIN; //disable CS for LIS2DH // required to read to clear the DRDY1 line so interrupt will work // read xy and z axis data (which clears interrupt) CSa_PxOUT &= ~CSa_PIN; // Set CS enabled for LIS2DH UCA0TXBUF = OUT_X_L |spiReadBurstbits; __delay_cycles(6*2);//assumes SCLK = SPI CLK) min=4 based on fastest compiler option (scoped) UCA0TXBUF = 0x00; __delay_cycles(8*2); //Initiate Transmit characters by transfer into TX buffer, /assumes SCLK = SPI CLK) UCA0TXBUF = 0x00; __delay_cycles(8*2); aX[0] = UCA0RXBUF; // Store data UCA0TXBUF = 0x00; __delay_cycles(8*2); aX[1] = UCA0RXBUF; // Store data UCA0TXBUF = 0x00; __delay_cycles(8*2); aY[0] = UCA0RXBUF; // Store data UCA0TXBUF = 0x00; __delay_cycles(8*2); aY[1] = UCA0RXBUF; // Store data UCA0TXBUF = 0x00; __delay_cycles(8*2); aZ[0] = UCA0RXBUF; // Store data UCA0TXBUF = 0x00; __delay_cycles(8*2); aZ[1] = UCA0RXBUF; // Store data CSa_PxOUT |= CSa_PIN; //disable CS for LIS2DH // enable LIS2DH interrupts P1IFG &= ~(BIT7); // Clear flags P1IE |= (BIT7); // Enable I1 LIS2DH // SFRIE1 |= WDTIE; // Enable WDT interrupt __enable_interrupt(); // __bis_SR_register(LPM4_bits | GIE); // Enter LPM4, enable interrupts __no_operation(); // For debug //*************************************************************************************** //********************************** PROGRAM LOOP *************************************** //*************************************************************************************** // program loop // flow is controlled by flags while(1) { // ------------------------------ if interrupt for LIS2DH ----------------------------- //read the LIS2DH if (drdyFlg) { drdyFlg=0x00; //reset the flag accActiveFlg=0x01; //set flag to indicate we are getting interrupts from LIS2DH zPrev = zCurr; // save previous reading for comparison // read xy and z axis data (which clears interrupt) CSa_PxOUT &= ~CSa_PIN; // Set CS enabled for LIS2DH UCA0TXBUF = OUT_X_L |spiReadBurstbits; __delay_cycles(6*2);//assumes SCLK = SPI CLK) min=4 based on fastest compiler option (scoped) UCA0TXBUF = 0x00; __delay_cycles(8*2); aX[0] = UCA0RXBUF; // Store data UCA0TXBUF = 0x00; __delay_cycles(8*2); aX[1] = UCA0RXBUF; // Store data UCA0TXBUF = 0x00; __delay_cycles(8*2); aY[0] = UCA0RXBUF; // Store data UCA0TXBUF = 0x00; __delay_cycles(8*2); aY[1] = UCA0RXBUF; // Store data UCA0TXBUF = 0x00; __delay_cycles(8*2); aZ[0] = UCA0RXBUF; // Store data UCA0TXBUF = 0x00; __delay_cycles(8*2); aZ[1] = UCA0RXBUF; // Store data CSa_PxOUT |= CSa_PIN; //disable CS for LIS2DH __no_operation(); // For debug //raise interrupt flag (P2.1) to send info to raspberry pi P2OUT = P2OUT | BIT1; //set interrupt pin high UCA1CTLW0 &= ~UCSWRST; // **Initialize USCI state machine** // exact timing is based on the clocking from the RPi // if gets stuck here then the watchdog timer will time out // if RPi SPI is 2MHz then 4us per byte while (!(UCA1IFG & UCTXIFG)); // USCI_A0 TX buffer ready? UCA1TXBUF =aX[0]; //send byte while (!(UCA1IFG & UCTXIFG)); // USCI_A0 TX buffer ready? UCA1TXBUF =aX[1]; //send byte while (!(UCA1IFG & UCTXIFG)); // USCI_A0 TX buffer ready? UCA1TXBUF =aY[0]; //send byte while (!(UCA1IFG & UCTXIFG)); // USCI_A0 TX buffer ready? UCA1TXBUF =aY[1]; //send byte while (!(UCA1IFG & UCTXIFG)); // USCI_A0 TX buffer ready? UCA1TXBUF =aZ[0]; //send byte while (!(UCA1IFG & UCTXIFG)); // USCI_A0 TX buffer ready? UCA1TXBUF =aZ[1]; //send byte P2OUT = P2OUT & ~BIT1; //set interrupt pin low while (!(UCA1IFG & UCTXIFG)); // wait till last byte done sending __delay_cycles(8*2*4); // delay required to ensure last byte transfer is finished 4us allows for 1 byte @ 2MHZ SPI //get the last received byte led = UCA1RXBUF; //__delay_cycles(400); //delay 25us to ensure RPi done transfer 744us between samples UCA1CTLW0 |= UCSWRST; // **Put state machine in reset** (prevent bit shifting) //set the 7 segment display //turn off all LED segments P1OUT &= ~0x0E; //P1 1.2.3 P2OUT &= ~0x0C; //P2 2.3 P3OUT &= ~0x03; //P3 0,1 // 1 = P1.1+P1.2 if (led==0x01) {P1OUT |= 0x06;} // 2 = P1.3+P1.1+P3.0+P3.1+P2.2 if (led==0x02) {P1OUT |= 0x0A; P2OUT |= 0x04; P3OUT |= 0x03;} // 3 = P1.3+P1.1+P3.0+P1.2+P2.2 if (led==0x03) {P1OUT |= 0x0E; P2OUT |= 0x04; P3OUT |= 0x01;} // 4 = P2.3+P3.0+P1.1+P1.2 if (led==0x04) {P1OUT |= 0x06; P2OUT |= 0x08; P3OUT |= 0x01;} // 5 = P1.3+P2.3+P3.0+P1.2+P2.2 if (led==0x05) {P1OUT |= 0x0C; P2OUT |= 0x0C; P3OUT |= 0x01;} // 6 = P1.3+P2.3+P3.1+P2.2+P1.2+P3.0 if (led==0x06) {P1OUT |= 0x0C; P2OUT |= 0x0C; P3OUT |= 0x03;} // 7 = P1.3+P1.1+P1.2 if (led==0x07) {P1OUT |= 0x0E;} // 8 = P1.1+P1.2+P1.3+P2.2+P2.3+P3.0+P3.1 if (led==0x08) {P1OUT |= 0x0E; P2OUT |= 0x0C; P3OUT |= 0x03;} // 9 = P1.1+P1.2+P1.3+P2.2+P2.3+P3.0 if (led==0x09) {P1OUT |= 0x0E; P2OUT |= 0x0C; P3OUT |= 0x01;} // 0 = P1.1+P1.2+P1.3+P2.2+P2.3+P3.1 if (led==0x00) {P1OUT |= 0x0E; P2OUT |= 0x0C; P3OUT |= 0x02;} }// if drdyFlg //test to see if stuck with int high if (P1IN & BIT7) { P1IFG &= ~(BIT7); drdyFlg=1;} }//while program loop } //-------------------------------------------------------------------------------------------- //---------------------------------- INTERRUPT ROUTINES ------------------------------------- //-------------------------------------------------------------------------------------------- //********************************************************** //******************* WDT INTERRUPT ********************** // Watchdog Timer interrupt service routine //comes here when WDT expires #pragma vector=WDT_VECTOR __interrupt void WDT_ISR(void) { //wdtCnt--; //decrement counter // see if we got interrupts from the LIS2DH during wdt interval if (accActiveFlg) {accActiveFlg=0x00;} //activity OK, just reset flag else { PMMCTL0 |= PMMSWBOR; //cause a software brown out reset } // NOTE : GO DIRECTLY TO LPM4 DO NOT WANT TO AFFECT TIMING BASED ON LIS2DH 0.1 INTERVALS __bis_SR_register_on_exit(LPM4_bits | GIE); // Enter LPM4, enable interrupts } //**************************************************************** //********************** PORT1 INTERRUPT ************************* //interrupt from the I1(p1.7) #pragma vector=PORT1_VECTOR __interrupt void port1_ISR (void) { //P1IE &= ~(BIT7); //Disable interrupt P1IFG &= ~(BIT7); //Clear I1 flag drdyFlg = 0x01; //set the flag to get main routine to service //disable LPM4 and interrupt on exit, so clocks will keep running __bic_SR_register_on_exit(CPUOFF | GIE); // Equivalent to exit in LPM0 with cpu clk } //**************************************************************** //********************** PORT2 INTERRUPT ************************* // this interrupt will alway happen between LIS2DH interrupts and be done before next one //interrupt from the GDO0 pin #pragma vector=PORT2_VECTOR __interrupt void port2_ISR (void) { TA0CTL = TASSEL__ACLK | MC__STOP; // ACLK, Timer STOPPED //disable LPM4 and interrupt on exit, so clocks will keep running __bic_SR_register_on_exit(CPUOFF | GIE); // Equivalent to exit in LPM0 with cpu clk } //********************************************************** //******************* ADC INTERRUPT ********************** // ADC interrupt service routine /* #pragma vector=ADC_VECTOR __interrupt void ADC_ISR(void) { switch(__even_in_range(ADCIV,ADCIV_ADCIFG)) { case ADCIV_NONE: break; case ADCIV_ADCOVIFG: break; case ADCIV_ADCTOVIFG: break; case ADCIV_ADCHIIFG: break; case ADCIV_ADCLOIFG: break; case ADCIV_ADCINIFG: break; case ADCIV_ADCIFG: resultADC = ADCMEM0; // save the ADC result __bic_SR_register_on_exit(CPUOFF | GIE); // Equivalent to exit in LPM0 with cpu clk break; default: break; } } */ // *************************************************************** //***************** Timer0 INTERRUPT *************************** // Timer0_B0 interrupt service routine // not used #pragma vector = TIMER0_A0_VECTOR __interrupt void Timer0_A0_ISR (void) { //Pedometer does not use Rx, so should never get here //come here when Timer0 overflows TA0CTL = TASSEL__ACLK | MC__STOP; //ACLK, Timer STOPPED TA0CCTL0 &= ~CCIE; // TBCCR0 interrupt disabled // exits in previous state which was sleeping } // *************************************************************** // ***************** Timer B1 INTERRUPT *************************** // Timer B1 interrupt service routine // used for delay at start up #pragma vector = TIMER1_A0_VECTOR __interrupt void Timer1_A0_ISR(void) { TA1CTL = TASSEL__ACLK | MC__STOP; //ACLK, Timer STOPPED TA1CCTL0 &= ~CCIE; // TB1CCR0 interrupt disabled __bic_SR_register_on_exit(CPUOFF | GIE); // Equivalent to exit in LPM0 with cpu clk }